Regards,
Victor Berman
DASC Chair
-----Original Message-----
From: jbhasker@lucent.com <jbhasker@lucent.com>
To: siwg@vhdl.org <siwg@vhdl.org>
Date: Monday, June 29, 1998 12:04 PM
Subject: Yuppie! IEEE 1076.6 VHDL synthesis standard passes IEEE ballot
>Dear Working Group Member:
>
>(nothing like good news when you come back from a vacation to Disneyland
"the
>happiest place on earth")
>
>It is with great pleasure that I wish to inform you that the IEEE 1076.6
>Standard for VHDL Register Transfer Level Synthesis has passed the IEEE
>ballot.
>
>Total on ballot: 115
>% Returned: 78%
>% Affirmative: 88%
>
>Over the next few weeks, the ballot resolution committee (same as the
>pilot group) will be addressing the many comments recieved via the ballot.
>The committee will also look into addressing the concerns of the
>negative balloters. If significant changes are recommended by the
>ballot resolution committee, a second round of balloting will be done.
>If only minor changes are recommended, then no second round of balloting
>shall occur.
>
>Thanks for all your hard work in developing this standard.
>
>Regards,
>
>- J. Bhasker, Lucent Technologies (610-712-3983, jbhasker@lucent.com )
> Chair, IEEE 1076.6 VHDL Synthesis Interoperability Working Group
> Email: siwg@vhdl.org, URL: http://vhdl.org/siwg
>