~~~~~~~~~~~~~~~~~~~~ MEETING #1 ~~~~~~~~~~~~~~~~~~~~~~~~~
A CHDStd standards meeting will be held on Friday from 8:00am to
10:00am in room ** 349 ** (not 493) of the DAC99 convention facility.
Note that this is a joint IEEE and IEC TC93 CHDStd meeting.
Note that the term, 'CHDStd' stands for
Chip Hierarchical Design System - Technical Data
FYI, CHDStd is being standardized as
- IEEE P1510 (under the IEEE DASC
- IEC 62015 (under the IEC TC93)
The purpose and agenda of this CHDStd meeting will be to
- Review what the CHDStd standard consists of - a general briefing
about CHDStd
- Discuss changes being requested to the definition of CHDStd
- Discuss the steps and status underway for standardizing CHDStd,
both within the IEEE DASC, SI2, and the IEC (under TC93 - Design
Automation)
- Request participation in balloting for CHDStd
- Answer any questions on CHDStd
Contact either of the two 'owners' of CHDStd for more information:
- Steve Grout, SEMATECH - phone 512-356-7071, steve.grout@sematech.org
- Don Cottrell, SI2 - phone 512-342-2244 (X22), cottrell@si2.org
You may get more information on CHDStd at DAC99 by visiting the
SI2 booth or the www.si2.org/CHDStd website.
---------------------------
In addition to the above standards meeting, the following are
related meetings:
~~~~~~~~~~~~~~~~~~~~ MEETING #2 ~~~~~~~~~~~~~~~~~~~~~~~~~
HARNESSING THE PHYSICS OF SMALL -
Complexity and Integration Issues of 130-100nm Design
Wednesday: DAC-99 Birds of Feather
Time: 6 - 7:30pm Organizers: Si2, Sematech
Room: Birds of Feather location will be
announced at DAC.
Panelists:
Bill Joyner (SRC) : ITRS'99 project design problems.
Paul Weil (WeilCAD) : 100nm EDA Roadmap Report/Design of Microprocessors
Joe Morrell (IBM) : CHDStd and how it relates to the need
Ted Vucurevich (Cadence): Cadence's approach to CHDStd
John Darringer (IBM) : Perspective of real user needs
Bill Grundmann (Compaq) : Perspective of real user needs
Terry Blanchard (HP) : Perspective of real user needs
Join fellow users from semiconductor and system companies
going over design problems coming with 130nm and later feature
size technologies. How can we harness solutions for those
problems, especially for our more challenging designs?
The panel will first include cover of some of design problems
being forecasted such as small feature size, gate length, and
much higher clock cycles. Several Using company panelists
will go over some of the issues: tool integration, growing
design complexity, increasingly difficult design convergence
and verification, growing number of design variables and
constraints, data growing exponentially, and the need for more
robust iterative design flows with growing emphasis on
redesign. Several initiatives and strategies will then be
considered that are believed to apply to system on a chip
(SoC) constraint-driven design (SoCAD),
including the CHDStd standard.
~~~~~~~~~~~~~~ Meeting #3 ~~~~~~~~~~~~~~~
SCALING THE GIGAHZ CURVE
Do we need Evolutionary or Revolutionary approaches?
Tuesday 6/22/99
Time: 8:00-9:00am
Location: Room 260-262, Ernest N. Morial Convention Center
New Orleans, LA
Organizers: SEMATECH and IEEE Design&Test of Computers
Panelists:
Lawrence Arledge : SRC
Jeff Burns : IBM
Jason Cong : University of California, LA
Bill Grundmann : Compaq
Wonjae Kang : Intel
John McBride : Hewlett Packard
Nagaraj NS : Texas Instruments
Technology roadmap for semiconductors show that processor designs
are poised to rapidly scale the gigahz curve in next five years.
Technologies in the range of 100nm, copper/low-k dielectrics for
interconnect, alternative processes such as SOI are being explored
to achive speed goals. With many second-order effects taking
increased significance, it makes one wonder if a revolutionary
approach is needed to address conflicting careabouts. This panel
will discuss key technical challenges and provide perspectives on
timing verification, clocking schemes, signal integrity issues,
design verification, packaging, reliability concerns, and design
for manufacturability challenges.