Well Done! - IEEE standard for VHDL RTL Synthesis

Victor Berman (berman@eda.org)
Thu, 23 Sep 1999 10:53:57 -0400

Bhasker and SIWG:

I would like to congratulate all of you on a fine piece of work.
This effort required an outstanding level of focus so as not to get
distracted by all the "other" things that could have theoretically
gone into this specification. The SIWG under the able leadership
of j. Bhasker were surely tempted to solve all the existing problems
in today's synthesis world including raising the abstraction level,
and defining new semantics for behavioral and other higher level
synthesis domains.
However, even though they had the expertise to embark on such
a mission, they realized that a successful standard needs first and
foremost to be built on a solid set of semantics that can be universally
understood and agreed to by all participants. This specification goes
a long way toward achieving that goal and correcting the current chaotic
situation where the semantics of synthesis is tool defined rather than
language based.
There is certainly an opportunity to be discouraged by how long
and difficult it is to define and standardize a specification like this one,
but this opportunity is better spent on celebrating the significant
progress that has been made and looking forward to more good work
in the future.

Well Done!

Victor Berman
DASC Chair