Subject: DASC Scope
From: Evan Lavelle (eml@riverside-machines.com)
Date: Wed Nov 12 2003 - 01:48:33 PST
My concern is pretty simple: what is the DASC actually *for*, and is the
current scope robust enough for the future? I think there are major
problems in both these areas. This is what the scope says:
> The purpose of the DASC is to promote the development of standards in
> the Design Automation industry. Such standards are beneficial to the
> designers and users of tools in this industry since they provide a
> mechanism for defining common semantics for the operation of tools.
This was pretty simple when the DASC was primarily concerned with VHDL
and Verilog. However, there's now an 'e' group, and there are likely to
be SystemVerilog and SystemC groups at some point. This means that the
DASC will have hundreds of members, many with conflicting agendas. This
is already starting to cause problems; one group recently attempted to
vote down a proposal to reference PSL in VHDL-200x. These votes were
rejected because they were received after the suspense date, but I'm not
convinced that any other mechanism could have been used to legitimately
disallow the votes.
Specific concerns:
1: the scope of DASC
--------------------
Is it the business of DASC to assist manufacturers or groups who wish to
standardise their own languages? If so, why? How does it benefit IEEE
members, and tool users? What are the metrics for deciding whether the
'approved by the IEEE' label should be granted to a particular group?
2: How does DASC handle conflicts of interests?
-----------------------------------------------
If it is in the interests of the IEEE to allow specific groups to use
the IEEE standardisation process, then are the DASC procedures robust
enough to ensure fairness in the event of a conflict of interests? I
don't think so. There is a provision that WG chairs can effectively
disallow corporate votes by combining them into a single vote. However,
this is no longer adequate - what would happen if an aggrieved party
demanded that all of Verisity's votes on P1647 were combined into a
single vote? 1647 would grind to a halt. If this sort of thing happens
then WG chairs currently interpret the rules as they see fit; this isn't
transparent, and is not due process.
3: Transparency
----------------
I may have missed something, but I don't actually know who's on the
Steering Committee, and who's on NesCom. The rest of us actually have
little or no influence on the standardisation process. However, if we're
going to be asked to vote on procedures then it would be nice to know
exactly who is on both the SC and NesCom, and what their affiliations
are. I also think it's absolutely essential that NesCom publishes their
reasons for accepting or rejecting a PAR, and their votes. This is not a
secret society. P1647 is now likely to become an IEEE standard at some
point. I have absolutely no objection to that, but I would like to know
how NesCom decided that this was a good thing. This will become much
more important for SystemVerilog and SystemC. For example, I noted
recently that a prominent member of NesCom expressed very robust views
on the desirability of C-based EDA languages in the press. We all have
our own opinions, but how is that particular opinion going to influence
OSCI's eventual PAR application?
Evan Lavelle
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