Re: Accellera and DASC

Gabe,

A statement like

"Cadence has commercial interests in making sure that the adoption of SystemVerilog is
both successful and deliberately slower than what both Synopsys and Mentor can achieve given the efficiency with which the CAG can
operate and the quality of the SystemVerilog 3.1a document."

may, strictly speaking, be factually correct, and it does not actually
say that Cadence is deliberately trying to slow SV, but that is the clear
implication.

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