RE: Accellera and DASC

Shalom,

I view the statement in your email to be contrary to our rules on discussion
of business issues within an IEEE standards development forum. Would you
please desist. Thank you.

Regards,

Peter Ashenden
DASC Chair

--
Dr. Peter J. Ashenden                        peter@ashenden.com.au
Ashenden Designs Pty. Ltd.                   www.ashenden.com.au
PO Box 640                                   Ph:  +61 8 8339 7532
Stirling, SA 5152                            Fax: +61 8 8339 2616
Australia                                    Mobile: +61 414 70 9106
> -----Original Message-----
> From: owner-stds-dasc@eda.org 
> [mailto:owner-stds-dasc@eda.org] On Behalf Of 
> Shalom.Bresticker@freescale.com
> Sent: Tuesday, 15 June 2004 02:58
> To: stds-dasc@eda.org
> Subject: Re: Accellera and DASC
> 
> 
> Gabe,
> 
> A statement like 
> 
> "Cadence has commercial interests in making sure that the 
> adoption of SystemVerilog is both successful and deliberately 
> slower than what both Synopsys and Mentor can achieve given 
> the efficiency with which the CAG can operate and the quality 
> of the SystemVerilog 3.1a document."
> 
> may, strictly speaking, be factually correct, and it does not 
> actually say that Cadence is deliberately trying to slow SV, 
> but that is the clear implication.
> 
> -- 
> Shalom Bresticker                         Shalom.Bresticker 
> @freescale.com
> Design & Reuse Methodology                            Tel: 
> +972 9  9522268
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> 
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>