Re: Accellera and DASC

Peter,
first of all thank you for the thoughtful comment regarding Shalom
statement.
Now, I would have thought that by now you would have found a way to rein in
the 1364 WG members. You never know what additional damage they may cause.
Obviously, especially the group of people that were also members of the
Accellera SystemVerilog working group really messed up and did not do a
proper job coordinating both efforts. May I remind you that the Chair of
the 1364 WG was also a board member of Accellera and thus fully aware of
what was going on both sides? And he is also the person that fostered the
introduction of P1647 under what can only be described as very suspect
circumstances. Their "noise" is interfering with the very good work you
have been doing mediating between the Computer Society and the CAG. I do
not want to have to deal with face saving on their part any more. I believe
I have been as kind as I can be, but I will not be kind if provoked one more
time.
Gabe
----- Original Message -----
From: "Peter Ashenden" <peter@ashenden.com.au>
To: <stds-dasc@eda.org>
Sent: Monday, June 14, 2004 5:36 PM
Subject: RE: Accellera and DASC

> Shalom,
>
> I view the statement in your email to be contrary to our rules on
discussion
> of business issues within an IEEE standards development forum. Would you
> please desist. Thank you.
>
> Regards,
>
> Peter Ashenden
> DASC Chair
>
> --
> Dr. Peter J. Ashenden peter@ashenden.com.au
> Ashenden Designs Pty. Ltd. www.ashenden.com.au
> PO Box 640 Ph: +61 8 8339 7532
> Stirling, SA 5152 Fax: +61 8 8339 2616
> Australia Mobile: +61 414 70 9106
>
>
> > -----Original Message-----
> > From: owner-stds-dasc@eda.org
> > [mailto:owner-stds-dasc@eda.org] On Behalf Of
> > Shalom.Bresticker@freescale.com
> > Sent: Tuesday, 15 June 2004 02:58
> > To: stds-dasc@eda.org
> > Subject: Re: Accellera and DASC
> >
> >
> > Gabe,
> >
> > A statement like
> >
> > "Cadence has commercial interests in making sure that the
> > adoption of SystemVerilog is both successful and deliberately
> > slower than what both Synopsys and Mentor can achieve given
> > the efficiency with which the CAG can operate and the quality
> > of the SystemVerilog 3.1a document."
> >
> > may, strictly speaking, be factually correct, and it does not
> > actually say that Cadence is deliberately trying to slow SV,
> > but that is the clear implication.
> >
> > --
> > Shalom Bresticker Shalom.Bresticker
> > @freescale.com
> > Design & Reuse Methodology Tel:
> > +972 9 9522268
> > Freescale Semiconductor Israel, Ltd. Fax:
> > +972 9 9522890
> > POB 2208, Herzlia 46120, ISRAEL Cell:
> > +972 50 5441478
> >
> > [ ]Freescale Internal Use Only
> > [ ]Freescale Confidential Proprietary
> >
> >
>
>
Received on Mon Jun 14 20:07:04 2004