disagreement on re-writing of PAR for 1364

Cliff,

Your statement regarding the re-writing of the PAR for 1364 is
misleading. At the 1364 meeting at DAC I proposed to modify both PAR
1800 and 1364 only in order to ensure strong co-operation between the
two groups and certainly not to weaken it in any ways, let alone to
close it down as you suggested during that meeting.

At that meeting we all favored a fast standardization of
SystemVerilog, but not to the detriment of Verilog 2001, upon which
System Verilog is built and which has infinitely more real users than
SystemVerilog currently has, and which is a joint IEEE/IEC standard
and needs the unequivocal support of the IEEE under which it became a
standard. Any irresponsible action of weakening the support for a
widely used standard such as Verilog will do little to alleviate the
concerns of companies such as IBM, NEC, Cadence, Verisity, and other
members of Accellera who did not agree with Accellera's current
approach regarding the standardization of SystemVerilog.

The proposal under consideration at the meeting was to standardize
SystemVerilog within the 1800 working group as soon as possible and
have all other enhancements to the language be developed under 1364 in
close co-operation with 1800.

Sincerely,

Alec Stanculescu

> Hi, All -
>
> A few comments of clarification.
>
> I have shared Shalom's frustration but have had a change of heart based on
> what I have seen in recent weeks. Unfortunately, as a friend to Shalom, I
> have done a lousy job of communicating to him what I have learned about the
> process from other meetings that I have attended in recent weeks.
>
> As a long-time IEEE Verilog, IEEE Verilog RTL Synthesis and Accellera
> SystemVerilog participant, I hope to encourage my valued colleagues, like
> Shalom, to continue participation and convince them that their
> participation will have a great impact.
>
> More comments below.
>
> At 02:16 AM 7/1/2004, Shalom.Bresticker@freescale.com wrote:
> >
> >I freely admit that I am angry and bitter.
> >
> >Consider what has happened and how it has been handled.
> >Consider how it appears to someone looking in from the outside.
> >I'll explain below.
> >
> >If it had been handled differently, maybe I would not react so harshly.
>
> True. Different handling could have made a difference.
>
> There have certainly been more politics on all sides in this process than I
> have ever seen before.
>
> As was stated in my DAC presentation, SystemVerilog has more potential to
> rearrange EDA simulation, synthesis & verification market shares than any
> other tool change seen in the past decade. In my opinion, this is why the
> politics have been so intense this time around.
>
> At times, the media has made this out as a battle between EDA vendors, but
> the more I dig into this, the more I see push from power-users to get
> Accellera to rapidly IEEE standardize SystemVerilog and the power-users
> have expressed fear that all of our relatively small 1364 enhancement
> proposals could slow down SystemVerilog standardization. I have shared this
> concern myself.
>
> >Consider the following:
> >
> >1. Accellera states it will withdraw its donation if the donation gets
> >in any way to the 1364 WG. There's first-hand testimony about that.
> >I think that could easily be called 'blackmail'.
>
> Agreed that it had a "blackmailish" look from a 1364 perspective, but from
> a rapid-adoption perspective, 1364 looked like a bottleneck. If you are a
> SystemVerilog user, you want fast-track adoption and you look for ways to
> make it happen. Unfortunately, the most viable way to accomplish that goal
> was to bypass 1364 altogether, OR ask 1364 to change its standard
> procedure, which made for poor public relations.
>
> >I would add also the scandalous way that Stu Sutherland was treated,
> >in the way he was fired from the SV editorship.
>
> I agree that this could have been handled much more diplomatically.
>
> >2. DASC-SC's response is to decide to dissolve the current 1364 WG and
> >move P1364 to the new SV WG, while reducing its PAR to errata-fixing.
> >That certainly appears like capitulation to blackmail.
>
> We actually held a meeting at DAC with Peter Asheden, Mike McNamara, Stu
> Sutherland, myself and many other VSG members and observers. In my opinion,
> we largely agreed that changing the PAR was probably a good idea. A number
> of us noted that we were missing Cadence representation, Shalom Bresticker
> and James Markevitch, among others, from the meeting. We had wished that
> they could have participated in the meeting, but I neglected to pass
> details to Shalom and others after the meeting. My apologies to Shalom and
> others.
>
> >3. Not only that, DASC-SC does this without talking to the current WG,
> >discussing and explaining. Nobody says anything to us, it's all done
> >behind our back. We have to learn everything from the media.
> >That's people mismanagement at its worst. No one even
> >comes to tell us, "Thank you for your efforts in the past."
>
> Same notes as above.
>
> A "thank you" certainly would have been a good diplomatic and courteous move.
>
> For the record, I have greatly valued Shalom's participation on the VSG
> over the years. He has certainly been one of the most dedicated members of
> the VSG. I hope to get him involved in SystemVerilog.
>
> >4. There has been no effort to preserve our participation. One might
> >think that people that have worked on 1364 for years might have something
> >valuable to contribute.
>
> There is certainly a movement within the P1800 group to include more expert
> participation, like Shalom's.
>
> >5. The secrecy of the new WG. Sure it's supposedly open.
> >Sure observers are supposedly welcome. But has there been a public call for
> >participation? Have today's meeting details in Germany been publicly
> >published? And it's still not clear how its chairman was appointed.
>
> A public call for participation will be going out. Anyone could have
> attended the Germany meeting. I asked the P1800 chair for dial-in
> information and he sent it to me. I think the problem that the group has
> right now is there is no official website or email list for the group.
>
> I believe the current interim chair, Johny Srouji of Intel-Israel, was
> appointed as part of the P1800 proposal submission from Accellera to the
> IEEE. New officers will be voted (entity-based voting) within the P1800
> group in the next couple of months. I would not be surprised to see Johny
> officially elected because he has been very active as one of the Accellera
> SystemVerilog chairs and has performed very well in that capacity. I must
> admit, I do worry about Israeli participants of any type :-) :-) :-)
>
> >Ah, the hell with it.
> >Like others have said, I know where I'm not wanted.
>
> Your knowledge is flawed! ;-)
>
> I hope to have your continued valuable participation.
>
> In my opinion, the standards process will be closer to what we have seen in
> the Accellera SystemVerilog effort. Subcommittees will have participants
> with individual votes and no SA-Entity Membership Requirements. Proposals
> from the subcommittees will then be proposed to the P1800 committee for
> final vote. Most of the technical discussion will happen within the subgroups.
>
> Also in my opinion, the other difference will probably be that the current
> list of 1364 enhancements will be largely postponed until a later revision
> while SystemVerilog is put on a fast-track path to IEEE standardization.
> Just my opinion from what I have observed.
>
> >You can bet I won't renew my DASC membership next year.
>
> Your choice, but be aware that I have been very impressed with Peter
> Asheden and the way he has skillfully navigated this process to merge the
> Verilog efforts.
>
> I am encouraged that we finally have all of the Verilog efforts under one
> organization and I hope this leads to one set of meetings as opposed to the
> two sets that I have been attending for the past few years.
>
> >--
> >Shalom Bresticker Shalom.Bresticker @freescale.com
>
> I hope this helps.
>
> Regards - Cliff
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, SystemVerilog, Synthesis and Verification Training
>
>
Received on Thu Jul 1 13:05:33 2004