Re: Vote on revised P1800 (SystemVerilog) PAR (resend)

[Stan, I mailed the following message on April 2 but received no
response so I am resending it, hoping to receive answers before
casting my vote. Thanks! -- A. Piziali]

Stan, you wrote:

> At the April 1, 2010 DASC meeting, Karen Pieper presented the draft
> revised P1800 (SystemVerilog) PAR that can be found at ... The DASC
> will vote via email on whether to approve this draft revised PAR.
> Please send your vote via return email to me at stanleyk@cadence.com
> <mailto:stanleyk@cadence.com>. Any questions can be asked via this
> reflector.

I have several questions and comments:

   (1) In sect. 3.1, why is the name of the chair "last name, first
       name" while the name of the vice chair is the reverse?

   (2) In sect. 5.4, why are "Semiconductor," "System Design" and
       "Errata" capitalized? They are not proper nouns in this context.

   (3) Will the punctuation errors in sect 5.5 be corrected before
       submission? For example:

           Examples of these disciplines are, design specification,
           assertion ...

   (4) In sect. 7.1, "Working Groups" should not be capitalized for the
       same reason as above. It should read "The purpose of this PAR
       clearly states the intent to co-exist with the results of the
       standards produced by these working groups ..."

-- 
	Andrew Piziali, <andy@piziali.dv.org>, +1-214-455-8577
	Skype andrew_piziali
"If you have to learn about ESL, you cannot ask for better instructors.
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